Metal features of a semiconductor device and methods for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuan-Kan Hu, Tsung-Kai Chiu, Wei-Yen Woon, Szuya Liao, Ku-Feng Yang
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Abstract
A method is provided that includes depositing a catalyst layer along a surface of the opening and performing a selectivity enhancement process. The selectivity enhancement process alters a deposition rate of a metal component on at least one region of the catalyst layer. The metal component is deposited on the catalyst layer. Exemplary selectivity enhancement processes include a self-assembled monolayer (SAM), introducing an accelerator, and/or introducing a suppressor.
Claims20
A method, comprising:
- providing an opening above a semiconductor substrate;
- depositing a catalyst layer along a surface of the opening;
- performing a selectivity enhancement process, wherein the selectivity enhancement process alters a deposition rate of a metal component on at least one region of the catalyst layer;
- and
- depositing the metal component on the catalyst layer.
A method, comprising:
- forming a structure including:
- a first fin structure including a channel region having a plurality of channel layers interleaved by a plurality of sacrificial layers,
- a source/drain region of the first fin structure adjacent the channel region, and
- a dummy gate stack over the channel region;
- removing the dummy gate stack and the plurality of sacrificial layers in the channel region to form an opening;
- forming a catalyst layer in the opening;
- depositing a metal layer over the catalyst layer and in the opening, wherein the depositing the metal layer includes performing a selectivity enhancement process introducing at least one of a self-assembled monolayer, accelerator components, or suppressor components.
A method of fabricating a semiconductor structure, the method comprising:
- providing a vertical stack of channel layers disposed over a substrate, wherein the vertical stack includes a first plurality of channel layers, a middle layer over the first plurality of channel layers, and a second plurality of channel layers over the middle layer;
- forming a first gate structure wrapping around each channel layer of the first plurality of channel layers and a second gate structure wrapping around each channel layer of the second plurality of channel layers, wherein the first gate structure is associated with a first transistor type and the second gate structure is associated with a second transistor type, wherein forming the first gate structure includes making a seam between a first channel layer and a second channel layer.
Dependencies are inferred from the claim text.