Metal hybrid charge storage structure for memory
AssigneeIntel NDTM US LLC
InventorsGuangyu Huang, Dipanjan Basu, Meng-Wei Kuo, Randy Koval, Henok Mebrahtu, Minsheng Wang, Jie Li, Fei Wang, Qun Gao, Xingui Zhang, Guanjie Li
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Abstract
Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.
Claims20
A memory cell, comprising:
- a control gate;
- a conductive channel;
- and
- a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer, wherein the polysilicon layer is positioned between the metal layer and the conductive channel, the charge storage structure is coupled to the control gate via two dielectric layers, a first dielectric layer of the two dielectric layers contacts the polysilicon layer of the charge storage structure, and a second dielectric layer of the two dielectric layers directly contacts both the polysilicon layer and the metal layer of the charge storage structure via a plurality of sides of each of the polysilicon layer and the metal layer.
A computing system, comprising:
- a motherboard;
- a processor coupled to the motherboard;
- and
- a memory device coupled to the motherboard, wherein the memory device includes a plurality of memory cells, and wherein one or more of the memory cells includes:
- a control gate,
- a conductive channel, and
- a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer, and wherein the polysilicon layer is positioned between the metal layer and the conductive channel, the charge storage structure is coupled to the control gate via two dielectric layers, a first dielectric layer of the two dielectric layers contacts the polysilicon layer of the charge storage structure, and a second dielectric layer of the two dielectric layers directly contacts both the polysilicon layer and the metal layer of the charge storage structure via a plurality of sides of each of the polysilicon layer and the metal layer.
A method of fabricating a memory cell, the method comprising:
- coupling a charge storage structure to a control gate, wherein the charge storage structure includes a polysilicon layer and a metal layer;
- and
- coupling a conductive channel to the charge storage structure, wherein the polysilicon layer is positioned between the metal layer and the conductive channel, the charge storage structure is coupled to the control gate via two dielectric layers, a first dielectric layer of the two dielectric layers contacts the polysilicon layer of the charge storage structure, and a second dielectric layer of the two dielectric layers directly contacts both the polysilicon layer and the metal layer of the charge storage structure via a plurality of sides of each of the polysilicon layer and the metal layer.
Dependencies are inferred from the claim text.