Method for manufacturing a super flash memory

A method for manufacturing a semiconductor device super flash memory, comprising steps of:

• step 1:
• providing a semiconductor substrate, forming first gate structures on the semiconductor substrate, and forming a channel region in the semiconductor substrate covered by the first gate structures;
• step 2:
• performing a first etching process to etch the semiconductor substrate on at least one side of each first gate structure to a certain depth and form a first groove, wherein a bottom surface of each first gate structure, a top surface of the semiconductor substrate, a top surface of the channel region, and a top surface of the first groove are flat, a bottom surface of the first groove is located below the top surface of the semiconductor substrate, and a bottom surface of the channel region is located below the top surface of the semiconductor substrate;
• and
• step 3:
• performing a stress memorization process, comprising the following sub-steps:
• step 31:
• forming a stress dielectric layer, the stress dielectric layer covering a peripheral surface of each first gate structure and being filled in the first groove;
• step 32:
• performing annealing to transfer a stress of the stress dielectric layer to the channel region, the stress in the channel region after stress transfer being increased in the process of stress transfer by using a characteristic that the stress dielectric layer located in the first groove laterally acts on the channel region;
• and
• step 33:
• removing the stress dielectric layer,
• wherein, in step 1, each first gate structure is a word line gate of a flash memory cell of the super flash memory;
• and
• in step 2, the first groove is located in a source region side of the first gate structure, the first etching process is an over-etching process of a source contact etching process, the source contact etching process firstly etches a first dielectric layer between adjacent first gate structures to form a source contact opening and then over-etches the semiconductor substrate at a bottom of the source contact opening to form the first groove, and the first groove is used as a part of the source contact opening,
• wherein, after step 3, the method for manufacturing the super flash memory further comprises the following steps:
• forming a source region in the semiconductor substrate at a bottom of the first groove;
• and
• forming a floating gate and a source line in the source contact opening, wherein
• in a transverse direction, the floating gate is located between the first gate structure and the source line;
• the floating gate and a side surface of the source region side of the first gate structure are isolated by a first inter-gate dielectric layer, and the first inter-gate dielectric layer comprises the first dielectric layer;
• the floating gate and the source line are isolated by a second inter-gate dielectric layer;
• a bottom of the source line is in direct contact with the source region;
• a bottom section of the floating gate is located in the first groove, and the bottom surface of the floating gate and the semiconductor substrate are isolated by a floating gate dielectric layer;
• during writing, the source line is simultaneously used as a control gate, and under the control of the control gate, electrons in the channel region are implanted into the bottom section of the floating gate under an effect of a transverse electric field;
• and
• a top surface of the floating gate is higher than a top surface of the source line.