Network transceiver with VGA channel specific equalization

A signal processing method, comprising:

• amplifying received signals at a plurality of variable gain amplifiers (VGAs);
• receiving amplified signals from the plurality of VGAs at each set of at least two sets of analog digital converters (ADCs), each set including a plurality of ADCs coupled to a respective output of a corresponding one of the plurality of VGAs, wherein a first set of the at least two sets of ADCs is arranged in at least a first VGA-specific channel and a second set of the at least two sets of ADCs is arranged in at least a second VGA-specific channel;
• and
• receiving an ADC sample signal from each of the plurality of ADCs at a clock data recovery (CDR) circuit coupled to each of the plurality of ADCs, and in response, generating a channel timing signal and an ADC timing signal, the channel timing signal alternating between the first VGA-specific channel and the second VGA specific channel, and the ADC timing signal including pulses that increment through each of the plurality of ADCs in each set of the at least two sets of ADCs.