Operation stage of pipeline analog-to-digital converter and analog-to-digital converter thereof

An operation stage of a pipeline analog-to-digital converter (pipeline ADC), wherein the operation stage is configured to generate a first output signal and a second output signal according to a first input signal and a second input signal, the first input signal is a common-mode voltage plus a voltage difference, and the second input signal is the common-mode voltage minus the voltage difference, the operation stage comprising:

• a voltage conversion circuit configured to generate an intermediate voltage according to the first input signal, the second input signal, and the common-mode voltage;
• a plurality of comparators configured to compare the intermediate voltage with N times a first reference voltage to generate a digital signal, wherein N is greater than or equal to negative one and less than or equal to one;
• a multiplexer coupled to the comparators and configured to generate a second reference voltage and a third reference voltage according to the digital signal;
• and
• a multiplication circuit configured to generate the first output signal and the second output signal according to the first input signal, the second input signal, the second reference voltage, and the third reference voltage;
• wherein the intermediate voltage is the common-mode voltage plus M times the voltage difference or the common-mode voltage minus M times the voltage difference, M is two to the power of R, and R is a positive integer.