Metastability error detection and BER improvement technique in pipelined ADCs

A pipelined analog-to-digital converter (ADC) comprising:

• a first ADC path including:
• a first stage ADC including a flash ADC and a first amplifier coupled to the flash ADC, the first amplifier having an input and an output;
• a second stage ADC having an input coupled to the output of the first amplifier, and having an output;
• a second amplifier having an input and an output;
• and
• a third stage ADC having an input coupled to the output of the second amplifier;
• a second ADC path coupled to the input of the first amplifier, and having an output;
• a metastability comparator having an input coupled to the flash ADC, and having an output;
• a logic circuit having an input coupled to the output of the metastability comparator and having an output;
• and
• a path selection circuit having a first input coupled to the output of the second stage ADC, having a second input coupled to the output of the second ADC path, having a select input coupled to the output of the logic circuit, and having an output coupled to the input of the second amplifier.

A system, comprising:

• a pipelined analog-to-digital converter (ADC) having a main path and an auxiliary path, wherein the main path includes:
• a first stage having an input, an output, a sampling switch, a flash ADC coupled to the sampling switch, a digital-to-analog converter (DAC) coupled to the flash ADC, and a first amplifier coupled to the DAC and the sampling switch;
• a second stage having an input coupled to the output of the first stage and to an input of a second amplifier;
• and
• a first backend ADC having an input coupled to an output of the second amplifier;
• and
• wherein the auxiliary path includes:
• a plurality of metastability comparators coupled to the flash ADC;
• selection circuitry coupled to an output of the DAC and the plurality of metastability comparators;
• a buffer having an input and an output, the input coupled to an output of the selection circuitry;
• and
• a second backend ADC coupled to the output of the buffer.