Device comprising a synchronization circuit for performing near field communication

A device configured to be able to communicate without contact with a reader by active load modulation, the device comprising:

• an input for receiving a first carrier signal emitted by the reader;
• an output for delivering a second carrier signal;
• and
• a synchronization circuit configured to synchronize the first carrier signal and the second carrier signal, the synchronization circuit comprising a phase-locked loop comprising:
• a first domain including:
• a digitally controlled oscillator configured to generate a signal at a given frequency;
• a first circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate, from the signal generated by the oscillator, the second carrier signal and a clock signal with a frequency comprised between the frequency of the second carrier signal and the frequency of the signal generated by the oscillator, the first domain being clocked by the first carrier signal;
• and
• a counter-divider configured to generate at the output:
• the second carrier signal from the signal generated by the oscillator so that the second carrier signal has a frequency reduced by a given factor compared to the frequency of the signal generated by the oscillator;
• the clock signal from the signal generated by the oscillator;
• and
• the information representative of the frequency of the signal generated by the oscillator by counting a number of clock strokes of the signal generated by the oscillator;
• a second domain including a second circuit configured to digitally compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator according to a result of the comparison, the second domain being clocked by the clock signal;
• and
• a frequency matching circuit between the first domain and the second domain, the frequency matching circuit configured to receive from the first domain information representative of the frequency of the signal generated by the oscillator at the frequency of the first carrier signal and to deliver the information to the second domain at the frequency of the clock signal, the frequency matching circuit including a FIFO register configured to receive as input the information representative of the frequency of the signal generated by the oscillator from the first domain of the phase-locked loop and for outputting the information representative of the frequency of the signal generated by the oscillator to the second domain of the phase-locked loop, the FIFO register being clocked at the input by the first carrier signal and being clocked at the output by the clock signal.