Wireless amplifier circuitry with non-linearity suppression

An amplifier comprising:

• a first transistor having a gate terminal configured to receive a radio-frequency signal, a source terminal, and a drain terminal, the gate terminal of the first transistor being configured to receive a first bias voltage that biases the first transistor in strong inversion;
• a second transistor having a gate terminal configured to receive the radio-frequency signal, a source terminal coupled to the source terminal of the first transistor, and a drain terminal coupled to the drain terminal of the first transistor, the gate terminal of the second transistor being configured to receive a second bias voltage that biases the second transistor in weak inversion;
• a degeneration inductor coupled to the source terminal of the first transistor;
• and
• a filter coupled to the source terminal of the first transistor and coupled to the source terminal of the second transistor.

Amplifier circuitry comprising:

• an amplification transistor configured to receive radio-frequency signals and to output corresponding amplified radio-frequency signals;
• an inductor having a terminal coupled to the source terminal of the amplification transistor;
• and
• a distortion suppression circuit that is configured to suppress non-linearity distortion of the amplified radio-frequency signals and that includes a filter coupled to the source terminal of the amplification transistor, coupled to the inductor, and configured to provide a shorting path between the source terminal of the amplifier transistor and a supply voltage terminal to filter out a portion of a signal generated by the inductor.