Testing structure for an integrated chip having a high-voltage device

A method for forming an integrated chip (IC), the method comprising:

• receiving a workpiece comprising:
• a dielectric structure disposed on a first side of a semiconductor substrate;
• a conductive interconnect structure disposed in the dielectric structure, wherein the conductive interconnect structure comprises a plurality of metal layers, wherein a first metal layer of the plurality of metal layers is disposed nearer the semiconductor substrate than each of the other metal layers of the plurality of metal layers, wherein the first metal layer comprises a first conductive feature, wherein the conductive interconnect structure comprises a stack of conductive plates that are electrically coupled together, wherein the stack of conductive plates are electrically coupled to the first conductive feature, and wherein the first metal layer vertically separates the stack of conductive plates from the semiconductor substrate;
• and
• a shallow trench isolation (STI) structure disposed in the semiconductor substrate;
• a ring-shaped deep trench isolation (DTI) structure disposed in the semiconductor substrate, wherein the ring-shaped DTI structure contacts the STI structure, wherein the stack of conductive plates are disposed at least partially laterally within a perimeter of the ring-shaped DTI structure, and wherein the first conductive feature is at least partially laterally within a perimeter of the ring-shaped DTI structure;
• and
• forming a first dielectric structure on a second side of the semiconductor substrate opposite the first side of the semiconductor substrate;
• forming an initial trench penetrating the first dielectric structure and the semiconductor substrate, wherein the initial trench is formed laterally within the perimeter of the ring-shaped DTI structure, and wherein a surface of the STI structure defines a surface of the initial trench;
• forming a second dielectric structure along sidewalls of the initial trench and along the surface of the initial trench;
• extending the initial trench to the first conductive feature, thereby forming a back-side through substrate via (BTSV) trench that exposes the first conductive feature, wherein extending the initial trench comprises penetrating the second dielectric structure, the STI structure, and the dielectric structure;
• and
• forming a BTSV in the BTSV trench, wherein the BTSV is electrically coupled to the first conductive feature.

A method for forming an integrated chip (IC), the method comprising:

• receiving a semiconductor substrate;
• forming an interconnect structure on a first side of the semiconductor substrate, wherein the interconnect structure comprises a plurality of metal layers, wherein a first metal layer of the plurality of metal layers is disposed nearer the semiconductor substrate than each of the other metal layers of the plurality of metal layers;
• forming a shallow trench isolation (STI) structure in the semiconductor substrate;
• forming a ring-shaped deep trench isolation (DTI) structure in the semiconductor substrate, wherein the STI structure is arranged between the ring-shaped DTI structure and the interconnect structure;
• forming a dielectric structure on a second side of the semiconductor substrate opposite the first side of the semiconductor substrate;
• forming a trench through the dielectric structure, through the semiconductor substrate, and through the STI structure to expose a conductive feature of the first metal layer, wherein the trench is formed laterally within a perimeter of the ring-shaped DTI structure;
• and
• forming a backside through substrate via (BTSV) in the trench, wherein the BTSV is electrically coupled to the conductive feature of the first metal layer.