Multi-machine version independent hierarchical verification

A system comprising:

• a memory storing instructions;
• and
• a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
• receive a first model of a first one of the plurality of circuit blocks, the first model generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a plurality of verification tests performed by the first version of the verification tool as well as a first setup information associated with the first circuit block;
• in response to a determination that, for each of the plurality of the tests performed by the first version of the verification tool, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, regenerate portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design so as to generate a modified first model, wherein the regeneration of the portions of the first model is performed using the first setup information and the version number(s) of the test(s) to be run on the circuit design;
• link the modified first model to the circuit design;
• and
• perform verification of the circuit design using one of the received first model or the linked modified first model.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:

• receive a first model of a first one of the plurality of blocks, the first model generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a plurality of verification tests performed by the first version of the verification tool as well as a first setup information associated with the first block;
• in response to a determination that, for each of the plurality of the tests performed by the first version of the verification tool, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, regenerate portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design so as to generate a modified first model, wherein the regeneration of the portions of the first model is performed using the first setup information and the version number(s) of the test(s) to be run on the circuit design;
• link the modified first model to the circuit design;
• and
• perform verification of the circuit design using one of the received first model or the linked modified first model.