Dual cache architecture and logical-to-physical mapping for a zoned random write area feature on zone namespace memory devices
AssigneeMicron Technology, Inc.
InventorsPranam Shetty, Manoj Selvam, Adarsha P
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AssigneeMicron Technology, Inc.
InventorsPranam Shetty, Manoj Selvam, Adarsha P
Estimating the term…
A method includes allocating random write resources to a first portion of a zone having a range of LBAs and a cache storing data of the first portion of the zone. A write command is received including an LBA. The LBA is mapped to a PBA of the cache using a first L2P table. Each of one or more LBAs in the range of LBAs of the first portion of the zone is mapped to a corresponding PBA of the cache using entries of the first L2P table. A range of sequential LBAs of a second portion of the zone is mapped to a physical block of the zone. Each LBA of the range of sequential LBAs is accessed using an offset corresponding to a position of each LBA in the range of sequential LBAs of the second portion of the zone. The write command is executed at the PBA.
A method comprising:
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
A system comprising:
Dependencies are inferred from the claim text.