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US 12,481,523 B2Granted
Flexible logic unit adapted for real-time task switching
AssigneeSilicon Mobility SAS
InventorsLoïc Jean Dominique Vezier, Bruno Bernard Jacques Sallé, Anselme Joseph Francis Lebrun
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Abstract
The invention applies to the context of an electric machine system where the digital control is handled with a FPCU component. This applies to application domains like but not limited to the automotive domain. The invention enables fast and safe time sliced context switching for application tasks mapped in FLU e FPGA matrix, similar as for the task context switching in a microprocessor, with the goal to maximize the usage of all computation resources of the FLU over time.
Claims7
An arrangement, comprising
- A) a matrix with
- (a) a plurality of programmable logic units;
- (b) a plurality of data store and restore circuits, each data store and restore circuit of the plurality of data store and restore circuits comprising a logic input;
- a first one bit clocked storage element, connected to and configured to receive the logic input;
- a second one bit clocked storage element, configured to receive an output of the first one bit clocked storage element;
- and a switching element that is configured to selectively input the logic input or an output of the second one bit clocked storage element to the first one bit clocked storage element;
- wherein the plurality of data store and restore circuits are arranged such that the logic input of each data store and restore circuit of the plurality of data store and restore circuits is directly connected to an output of a programmable logic unit of the plurality of programmable logic units;
- and wherein an output of the first one bit clocked storage element of the plurality of data store and restore circuits is connected to an input of a programmable logic unit of the plurality of programmable logic units;
- wherein the programmable logic units and first one bit clocked storage elements are arranged in an array, the arrangement being adapted for sequential execution of at least two tasks;
- and
- B) a data memory, external to the matrix, wherein the data store and restore circuit is provided for
- (i) pre-loading values related to one task from the data memory into the data store and restore circuit and
- (ii) post-storing of values related to one task in the data store and restore circuit to the data memory, whereby the pre-loading and/or post-storing can be performed while another task is executed without disturbing the task execution.
10 more elements
Dependencies are inferred from the claim text.