User-level threading for simulating multi-core processor

A computer program product for improving an execution speed of a host multi-core simulator of a computer simulating a target multi-core processor that has a hierarchical architecture including multiple corelets per core that, in turn include multiple functional units, wherein the host multi-core simulator is implemented using multiple operating system (OS) threads, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by the computer to cause the computer to perform a method comprising:

• selecting, by the host multi-core simulator, one or more layers in the hierarchical architecture of the target multi-core processor to simulate on respective OS threads of the host multi-core simulator, based on a shortest estimated layer execution time determined by (1.0+t/c*s)/min (c, t), wherein c is a number of cores in the host multi-core simulator, t is a number of the multiple OS threads, and s is a coefficient to estimate a threading overhead;
• and
• respectively executing, from among the selected one or more layers, the OS threads on respective cores of the host multi-core simulator to perform a parallel simulation of the multiple functional units therein that frequently communicate with each other on one of the multiple OS threads based on a communication frequency threshold, by assigning and using a respective user-level thread for each of the multiple functional units from among a plurality of user-level threads with a parallel execution scheme for simulating each of the multiple functional units simultaneously by a respective one of a plurality of user-level threads, skipping, by the host multi-core simulator, synchronization for a communication conflict between any of the multiple functional units that are simulated on the same OS thread.

A computer processing system for improving an execution speed of a host multi-core simulator simulating a target multi-core processor that has a hierarchical architecture including multiple corelets per core that, in turn include multiple functional units, wherein the host multi-core simulator is implemented using multiple operating system (OS) threads, the computer processing system comprising:

• a memory device for storing program code therein;
• and
• a processor device operatively coupled to the memory device for running the program code to:
• select one or more layers in the hierarchical architecture of the target multi-core processor to simulate on respective OS threads of the host multi-core simulator, based on a shortest estimated layer execution time determined by (1.0+t/c*s)/min (c, t), wherein c is a number of cores in the host multi-core simulator, t is a number of the multiple OS threads, and s is a coefficient to estimate a threading overhead;
• and
• respectively execute, from among the selected one or more layers, the OS threads on respective cores of the host multi-core simulator to perform a parallel simulation of the multiple functional units therein that frequently communicate with each other on one of the multiple OS threads based on a communication frequency threshold, by assigning and using a respective user-level thread for each of the multiple functional units from among a plurality of user-level threads with a parallel execution scheme for simulating each of the multiple functional units simultaneously by a respective one of a plurality of user-level threads, skip synchronization for a communication conflict between any of the multiple functional units that are simulated on the same OS thread.