System and methods of reducing wideband series resonant clock skew
OwnerRiadul Islam, Dhandeep Challagundla +1inventors
InventorsRiadul Islam, Dhandeep Challagundla, Ignatius Bezzam
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OwnerRiadul Islam, Dhandeep Challagundla +1inventors
InventorsRiadul Islam, Dhandeep Challagundla, Ignatius Bezzam
Estimating the term…
A resonant clocking system for reducing wideband series resonant clock skew is provided. The resonant clocking system includes at least one Pulsed Series Resonance (PSR) driver, at least one clock gater, and at least one clock buffer. The PSR driver is connected with at least one on-chip inductor. The PSR driver receives a boosted-amplitude pulsed signal VSR that is generated using a matching pulse generator and at least one on-chip inductor connected with the at least one Pulsed Series Resonance (PSR) driver resonates with a capacitance of the resonant clocking system to generate a pulse signal RCLK. The at least one clock gater and the at least one clock buffer propagate the pulse signal RCLK to clock pins of resonant flip-flops. An inductance value of the at least one on-chip inductor is matched with a load capacitance of a corresponding branch capacitance using an inductor tuning technique to obtain equal frequency signals in all clock branches, thereby storing dissipated energy in a form of a magnetic field in the at least one on-chip inductor and reducing wideband series resonant clock skew.
A resonant clocking system for reducing wideband series resonant clock skew, comprising:
A resonant clock mesh system for reducing wideband series resonant clock skew, comprising:
A method for reducing wideband series resonant clock skew, comprising:
Dependencies are inferred from the claim text.