Low pin count scan with no dedicated scan enable pin
AssigneeSTMicroelectronics International N.V.
InventorsSandeep Jain, Shalini Pathak
Life of this patent
Estimating the term…
Abstract
According to an embodiment, a method for testing using scan chains, without an independent scan enable pin, is proposed. The method includes selectively indicating a capture phase and a load/unload phase for the scan chain based on an encoding of a scan enable signal in an expected signal and a masking signal; loading test parameters to the scan chain during the load/unload phase; operating the scan chain under functional mode during the capture phase; and generating an error signal based on comparing an output of the scan chain during an unload phase with the expected signal, wherein the masking signal is used to mask the output of the scan chain for cycles with invalid results.
Claims20
A method for testing using scan chains, without an independent scan enable pin, the method comprising:
- selectively indicating a capture phase and a load/unload phase for the scan chain based on an encoding of a scan enable signal in an expected signal and a masking signal;
- loading test parameters to the scan chain during the load/unload phase;
- operating the scan chain under functional mode during the capture phase;
- and
- generating an error signal based on comparing an output of the scan chain during an unload phase with the expected signal, wherein the masking signal is used to mask the output of the scan chain for cycles with invalid results.
A method for testing using scan chains without an independent scan enable pin, the method comprising:
- pre-loading a first number of shift cycles into a shift counter circuit, the first number of shift cycles corresponding to a test pattern set;
- pre-loading a second number of capture cycles into a capture counter circuit, the second number of capture cycles corresponding to the test pattern set;
- initiating a load/unload phase of the testing by maintaining an internally generated scan enable signal at a high logic level, wherein the shift counter circuit counts the pre-loaded number of shift cycles;
- transitioning the internally generated scan enable signal to a logic level in response to a completion of the pre-loaded count by the shift counter circuit, wherein the transitioning initiates a capture phase of the testing;
- and
- initiating a subsequent load/unload phase of the testing by transitioning the internally generated scan enable signal to the high logic level in response to a completion of the pre-loaded count by the capture counter circuit.
A method for testing using scan chains in a digital circuit without an independent scan enable pin, the method comprising:
- specifying a first pin assignment with N input pins and R merged input pins, N and R being integers, N corresponding to a number of input pins for carrying scan-in chain test data, and R corresponding to a number of input pins for carrying a merged expected test result and a masking instruction signal;
- specifying a second pin assignment with N input pins and M output pins, M being an integer and corresponding to a number of output pins for carrying scan-out chain test data;
- inserting a comparator circuit and a decoding logic circuit into the digital circuit;
- generating an N by M codec;
- integrating the N by M codec and inserting scan chains, wherein device registers are stitched into multiple scan chains and coupled between a compression circuit and a decompression circuit;
- and
- decoding an internally generated scan enable signal using one of the 2R states provided by the R merged input pins, wherein 3N states are decoded outputs from the decoding logic circuit.
Dependencies are inferred from the claim text.