Techniques for identification and correction of clock duty-cycle
AssigneeIntel Corporation
InventorsJohn R. Cherukuri, Roan M. Nicholson
Life of this patent
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Abstract
Embodiments herein relate to an apparatus comprising: a first circuit with a plurality of stages; and a second circuit communicatively coupled with the first circuit, wherein the second circuit includes: a plurality of tap lines, wherein respective tap lines of the plurality of tap lines are coupled between two stages of the plurality of stages; and the logic, wherein the logic is to identify, based on an average voltage measurement of at least one tap line, a status of a duty-cycle of a signal propagating through a stage of the first circuit. Other embodiments may be described and claimed.
Claims19
An apparatus comprising:
- a first circuit that is a high-speed serial input/output (I/O) with a plurality of stages having a signal of greater than 8 GHz propagating through at least one of the plurality of stages;
- and
- a second circuit communicatively coupled with the first circuit, wherein the second circuit includes:
- a plurality of tap lines, wherein respective tap lines of the plurality of tap lines are coupled between two stages of the plurality of stages;
- and
- logic, wherein the logic is to identify, based on an average voltage measurement of at least one tap line, a status of a duty-cycle of the signal propagating through the first circuit.
A circuit comprising:
- a plurality of tap lines, wherein respective tap lines of the plurality of tap lines are coupled between two stages of a plurality of stages of a first circuit that is a high-speed serial input/output (I/O) circuit with a plurality of stages having a signal of greater than 8 GHz propagating through at least one of the plurality of stages;
- and
- logic, wherein the logic is to identify, based on an average voltage measurement of at least one tap line, a status of a duty-cycle of a signal propagating through a stage of the first circuit.
One or more non-transitory computer-readable media comprising instructions that, upon execution of the instructions by a logic, are to cause the logic to:
- identify, based on a signal received from at least one tap line of a plurality of tap lines that are respectively coupled between stages of a plurality of stages of a first circuit that is a high-speed serial input/output (I/O) circuit with a plurality of stages having a signal of greater than 8 GHz propagating through at least one of the plurality of stages, an average voltage measurement of the first circuit at a point at which the at least one tap line is coupled to the first circuit;
- compare the average voltage measurement to a voltage threshold;
- and
- identify, based on the comparison, a status of a duty-cycle of the first circuit.
Dependencies are inferred from the claim text.