Programmable delay testing circuit

A built-in self-test (BIST) circuit comprising:

• a sampler register comprising a signal input configured to receive a signal to be delayed, a plurality of test result outputs, and a plurality of delay inputs that are each configured to be coupled to a respective delay output of a plurality of delay phases of an analog delay circuit, the sampler register being configured to
• output a sample signal indicating a relationship between the signal to be delayed and at least a final delay phase of the plurality of delay phases;
• a finite state machine circuit comprising a delay configuration output configured to be coupled to a delay configuration input of the analog delay circuit, and a plurality of test result inputs coupled to the plurality of test result outputs of the sampler register, the finite state machine circuit being configured to
• iterate through a plurality of selected delay values provided to the analog delay circuit at the delay configuration input to test the analog delay circuit,
• determine that the analog delay circuit passes the test by determining that the relationship matches a predetermined criterion in response to receiving the sample signal at the plurality of test result inputs, and
• output delay tuning data indicating a selected delay value of the plurality of selected delay values, the selected delay value being associated with matching the predetermined criterion;
• a test data register coupled to the finite state machine circuit, the test data register being configured to store status flags of the finite state machine circuit and the delay tuning data.

A method of testing an analog delay circuit of an integrated circuit, the method comprising:

• receiving a signal to be delayed at a signal input of the analog delay circuit, the analog delay circuit comprising a delay configuration input and a plurality of delay phases comprising an initial delay phase and a final delay phase;
• receiving the signal to be delayed at a signal input of a sampler register of the integrated circuit, the sampler register comprising a plurality of test result outputs and a plurality of delay inputs that are each coupled to a respective output of the plurality of delay phases;
• outputting from the sampler register a sample signal indicating a relationship between the signal to be delayed and at least the final delay phase of the plurality of delay phases;
• iterating through a plurality of selected delay values provided by a delay configuration output of a test circuit of the integrated circuit to the analog delay circuit at the delay configuration input to test the analog delay circuit, the test circuit comprising a plurality of test result inputs coupled to the plurality of test result outputs of the sampler register;
• and
• determining that the analog delay circuit passes the test in response to receiving the sample signal at the plurality of test result inputs by determining that the relationship matches a predetermined criterion.