Method for producing semiconductor wafers using a wire saw, wire saw, and semiconductor wafers made of monocrystalline silicon

A semiconductor wafer of monocrystalline silicon sawn from a monocrystalline silicon workpiece, having an upper side surface and a lower side surface, comprising

• a) a warp of less than 1.2 μm;
• b) a nanotopography of the upper side surface, expressed as THA25 10%, of less than 5 nm;
• and
• c) a subsurface-referenced nanotopography of the upper side surface of less than 6 nm, expressed as a maximum peak-to-valley distance on a subsurface and referenced to subsurfaces with an area content of 25 mm×25 mm, wherein sawing of the workpiece is achieved through a process comprising:
• feeding the workpiece through an arrangement of wires which are tensioned between wire guide rollers while being divided into wire groups and move in a running direction,
• producing kerfs when the wires engage the workpiece;
• for each of the wire groups, determining a placement error of the kerfs of the wire group;
• and
• for each of the wire groups, including a compensating movement of the wires of the wire group as a function of the determined placement error of the kerfs of the wire group, in a direction perpendicular to a running direction of the wires of the wire group during the feeding of the workpiece through the arrangement of wires by activating at least one wire group drive element.

A semiconductor wafer of monocrystalline silicon sawn from a monocrystalline silicon workpiece, having an upper side surface and a lower side surface, comprising

• a) a warp of less than 1.2 μm;
• b) a nanotopography of the upper side surface, expressed as THA25 10%, of less than 5 nm;
• and
• c) a subsurface-referenced nanotopography of the upper side surface of less than 6 nm, expressed as a maximum peak-to-valley distance on a subsurface and referenced to subsurfaces with an area content of 25 mm×25 mm, wherein sawing of the workpiece is achieved through a process comprising:
• feeding the workpiece through an arrangement of wires which are tensioned between wire guide rollers while being divided into wire groups and move in a running direction,
• producing kerfs when the wires engage the workpiece;
• for each of the wire groups, determining a placement error of the kerfs of the wire group;
• and
• for each of the wire groups, including a compensating movement of the wires of the wire group as a function of the determined placement error of the kerfs of the wire group, in a direction perpendicular to a running direction of the wires of the wire group during the feeding of the workpiece through the arrangement of wires by activating at least one wire group drive element;
• and
• polishing the semiconductor wafer,
• wherein the values of the warp a), nanotopography b), and subsurface-referenced nanotopography c) are those values measured after polishing the semiconductor wafer.