Resistive memory device and manufacturing method of the resistive memory device
AssigneeSK hynix Inc.
InventorIn Ku Kang
Life of this patent
Estimating the term…
Abstract
There are provided a resistive memory device and a manufacturing method of the resistive memory device. The resistive memory device includes: a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked; a hole penetrating the stack structure in a vertical direction; and a gate insulating layer, a channel layer, and a variable resistance layer, formed along sidewalls of the plurality of conductive layers, which are adjacent to the hole, and sidewalls of the plurality of interlayer insulating layers, which are adjacent to the hole.
Claims10
A resistive memory device comprising:
- a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked;
- a hole penetrating the stack structure in a vertical direction;
- and
- a gate insulating layer, a channel layer, and a variable resistance layer, formed along sidewalls of the plurality of conductive layers, which are adjacent to the hole, and sidewalls of the plurality of interlayer insulating layers, which are adjacent to the hole,
- wherein all of the sidewalls of the plurality of interlayer insulating layers, which are adjacent to the hole, have a concave shape and all of the sidewalls of the plurality of conductive layers, which are adjacent to the hole, have a flat shape.
A resistive memory device comprising:
- a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked;
- a hole penetrating the stack structure in a vertical direction;
- gate insulating layers disposed between the hole and the respective plurality of conductive layers;
- and
- a channel layer and a variable resistance layer, sequentially formed along sidewalls of the plurality of interlayer insulating layers, which are adjacent to the hole, and sidewalls of the gate insulating layers, which are adjacent to the hole,
- wherein the gate insulating layers correspond to respective ones of the plurality of conductive layers, and adjacent gate insulating layers are physically separated from each other by the channel layer in contact with the plurality of interlayer insulating layers.
Dependencies are inferred from the claim text.