Semiconductor device including a vertically stacked channel pattern and method for manufacturing the same

A semiconductor device, comprising:

• a substrate including a first active pattern and a second active pattern;
• a first channel pattern on the first active pattern, the first channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern spaced apart from one another and vertically stacked in a vertical direction, the vertical direction extending perpendicular to an upper surface of the substrate;
• a second channel pattern on the second active pattern, the second channel pattern including a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth semiconductor pattern spaced apart from one another and vertically stacked in the vertical direction;
• a first source/drain pattern connected to the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern;
• a second source/drain pattern connected to the fourth semiconductor pattern, the fifth semiconductor pattern, and the sixth semiconductor pattern;
• and
• a gate electrode extending from the first channel pattern to the second channel pattern,
• wherein the second source/drain pattern has a conductivity type that is different from a conductivity type of the first source/drain pattern,
• wherein the gate electrode includes a first portion, a second portion, and a third portion adjacent to each of the fourth semiconductor pattern, the fifth semiconductor pattern, and the sixth semiconductor pattern,
• wherein the first source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern in a horizontal direction, a second protrusion protruding toward the second semiconductor pattern in the horizontal direction, and a third protrusion protruding toward the third semiconductor pattern in the horizontal direction, the horizontal direction extending parallel to the upper surface of the substrate,
• wherein the second source/drain pattern includes a fourth protrusion protruding toward the first portion in the horizontal direction, a fifth protrusion protruding toward the second portion in the horizontal direction, and a sixth protrusion protruding toward the third portion in the horizontal direction,
• wherein a length of the second semiconductor pattern in the horizontal direction is greater than a length of the third semiconductor pattern in the horizontal direction, and
• wherein a length of the fifth semiconductor pattern in the horizontal direction is smaller than a length of the sixth semiconductor pattern in the horizontal direction.

A semiconductor device, comprising:

• a substrate including an active region;
• a device isolation layer defining an active pattern on the active region;
• a channel pattern and a source/drain pattern on the active pattern, the channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern spaced apart from one another and vertically stacked in a vertical direction, the vertical direction extending perpendicular to an upper surface of the substrate;
• a gate electrode on the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern;
• a gate insulating layer between the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern and the gate electrode;
• a gate spacer on a sidewall of the gate electrode;
• a gate capping pattern on a top surface of the gate electrode;
• an interlayer insulating layer on the gate capping pattern;
• an active contact electrically connected to the source/drain pattern through the interlayer insulating layer;
• a metal-semiconductor compound layer interposed between the active contact and the source/drain pattern;
• a gate contact passing through the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode;
• a first metal layer on the interlayer insulating layer, the first metal layer including a power wiring and first wirings electrically connected to the active contact and the gate contact, respectively;
• and
• a second metal layer on the first metal layer,
• wherein the second metal layer includes second wirings electrically connected to the first metal layer,
• wherein the source/drain pattern includes a first protrusion protruding toward the first semiconductor pattern in a horizontal direction, a second protrusion protruding toward the second semiconductor pattern in the horizontal direction, and a third protrusion protruding toward the third semiconductor pattern in the horizontal direction, the horizontal direction extending parallel to the upper surface of the substrate,
• wherein a length of the second semiconductor pattern in the horizontal direction is greater than a length of the third semiconductor pattern in the horizontal direction, and
• wherein a length of the first semiconductor pattern in the horizontal direction is greater than the length of the second semiconductor pattern in the horizontal direction.