Metal-insulator-metal structure and methods of fabrication thereof

A semiconductor device, comprising:

• a logic region;
• a memory region;
• a first dielectric layer extending from the logic region to the memory region;
• a second dielectric layer disposed above the first dielectric layer and extending from the logic region to the memory region;
• and
• a metal-insulator-metal (MIM) capacitor disposed in the memory region and stacked between the first dielectric layer and the second dielectric layer,
• wherein the MIM capacitor includes:
• a bottom electrode disposed on a top surface of the first dielectric layer, wherein the bottom electrode has a first sidewall,
• a top electrode disposed above the bottom electrode, wherein the top electrode has a second sidewall, wherein with respect to the top surface of the first dielectric layer the first sidewall forms a smaller angle than the second sidewall, and
• an insulating layer interposed between the bottom electrode and the top electrode, wherein the insulating layer covers the first sidewall of the bottom electrode, and the second dielectric layer covers and interfaces with the second sidewall of the top electrode.

A semiconductor device, comprising:

• a first electrode disposed over a top surface of a dielectric layer;
• an insulating layer disposed over the first electrode;
• a second electrode disposed over the insulating layer;
• a first via extending through the second electrode;
• and
• a second via extending through the first electrode,
• wherein:
• the first via includes a first sidewall having an upper portion, a middle portion, and a lower portion,
• the middle portion of the first sidewall directly contacts the second electrode, and
• with respect to the top surface of the dielectric layer, the middle portion of the first sidewall forms a smaller angle than the upper and lower portions of the first sidewall.