A semiconductor-element-including memory device that is a memory device in which in plan view on a substrate, a plurality of pages are arranged in a column direction, each of the pages being constituted by a plurality of memory cells arranged in a row direction,
- each of the memory cells included in each of the pages comprising:
- a semiconductor body that stands on the substrate in a vertical direction or that extends along the substrate in a horizontal direction;
- a first impurity region and a second impurity region that are disposed at respective ends of the semiconductor body;
- a gate insulator layer that is in contact with a side surface of the semiconductor body between the first impurity region and the second impurity region;
- a first gate conductor layer that partially or entirely covers the gate insulator layer;
- and
- a second gate conductor layer that is adjacent to the first gate conductor layer and that is in contact with a side surface of the gate insulator layer, wherein
- voltages applied to the first impurity region, the second impurity region, the first gate conductor layer, and the second gate conductor layer are controlled to perform a page erase operation of making some of a group of positive holes in the semiconductor body of each of the memory cells in a page among the pages disappear and decreasing the number of positive holes and to perform a page write operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a selected memory cell in a page among the pages, and
- a page read operation includes a refresh operation performed in parallel with a page read operation, in which the refresh operation maintains a state of the semiconductor body of the memory cell for which the page erase operation has been performed and a state of the semiconductor body of the memory cell for which the page write operation has been performed.