Receiver with pre-cursor intersymbol interference mitigation

A receiver comprising:

• equalizer circuitry having a first input, a second input, a third input, a fourth input, a fifth input, and an output;
• clock and data recovery (CDR) circuitry having a first input, a second input, and a clock output, the first input of the CDR circuitry coupled to the output of the equalizer circuitry;
• sampler circuitry having a first input, a second input, and an output, the first input of the sampler circuitry coupled to the output of the equalizer circuitry, the second input of the sampler circuitry coupled to the clock output of the CDR circuitry;
• adaptation circuitry having an input, a first output, a second output, and a third output, the input of the adaptation circuitry coupled to the output of the sampler circuitry, the first output of the adaptation circuitry coupled to the fourth input of the equalizer circuitry, the second output of the adaptation circuitry coupled to the fifth input of the equalizer circuitry;
• and
• clock adjustment circuitry having a first input, a second input, and an output, the first input of the clock adjustment circuitry coupled to the clock output of the CDR circuitry, the second input of the clock adjustment circuitry coupled to the third output of the adaptation circuitry;
• wherein the adaptation circuitry includes a clock adjustment controller having an input and an output, the clock adjustment controller configured to:
• receive a continuous-time linear equalizer (CTLE) index result;
• and provide a clock adjustment control signal to the clock adjustment circuitry responsive to the CTLE index result.

A system comprising:

• a transmitter;
• and
• a receiver in communication with the transmitter via a channel, the receiver including:
• equalizer circuitry having a first input, a second input, a third input, a fourth input, a fifth input, and an output;
• clock and data recovery (CDR) circuitry having a first input, a second input, and a clock output, the first input of the CDR circuitry coupled to the output of the equalizer circuitry;
• sampler circuitry having a first input, a second input, and an output, the first input of the sampler circuitry coupled to the output of the equalizer circuitry, the second input of the sampler circuitry coupled to the clock output of the CDR circuitry;
• adaptation circuitry having an input, a first output, a second output, and a third output, the input of the adaptation circuitry coupled to the output of the sampler circuitry, the first output of the adaptation circuitry coupled to the fourth input of the equalizer circuitry, the second output of the adaptation circuitry coupled to the fifth input of the equalizer circuitry;
• and
• clock adjustment circuitry having a first input, a second input, and an output, the first input of the clock adjustment circuitry coupled to the clock output of the CDR circuitry, the second input of the clock adjustment circuitry coupled to the third output of the adaptation circuitry;
• wherein the clock adjustment circuitry is configured to:
• receive a clock signal from the clock output at its first input;
• receive a clock adjustment control signal at its second input;
• and
• provide a delayed version of the clock signal at its output responsive to the clock signal and the clock adjustment control signal.

A system comprising:

• a transmitter;
• and
• a receiver in communication with the transmitter via a channel, the receiver including:
• equalizer circuitry having a first input, a second input, a third input, a fourth input, a fifth input, and an output;
• clock and data recovery (CDR) circuitry having a first input, a second input, and a clock output, the first input of the CDR circuitry coupled to the output of the equalizer circuitry;
• sampler circuitry having a first input, a second input, and an output, the first input of the sampler circuitry coupled to the output of the equalizer circuitry, the second input of the sampler circuitry coupled to the clock output of the CDR circuitry;
• adaptation circuitry having an input, a first output, a second output, and a third output, the input of the adaptation circuitry coupled to the output of the sampler circuitry, the first output of the adaptation circuitry coupled to the fourth input of the equalizer circuitry, the second output of the adaptation circuitry coupled to the fifth input of the equalizer circuitry;
• and
• clock adjustment circuitry having a first input, a second input, and an output, the first input of the clock adjustment circuitry coupled to the clock output of the CDR circuitry, the second input of the clock adjustment circuitry coupled to the third output of the adaptation circuitry;
• wherein the clock adjustment circuitry is configured to:
• receive a clock signal from the clock output at its first input;
• receive a clock adjustment control signal at its second input;
• and
• provide a voltage offset version of the clock signal at its output responsive to the clock signal and the clock adjustment control signal.

A system comprising:

• a transmitter;
• and
• a receiver in communication with the transmitter via a channel, the receiver including:
• equalizer circuitry having a first input, a second input, a third input, a fourth input, a fifth input, and an output;
• clock and data recovery (CDR) circuitry having a first input, a second input, and a clock output, the first input of the CDR circuitry coupled to the output of the equalizer circuitry;
• sampler circuitry having a first input, a second input, and an output, the first input of the sampler circuitry coupled to the output of the equalizer circuitry, the second input of the sampler circuitry coupled to the clock output of the CDR circuitry;
• adaptation circuitry having an input, a first output, a second output, and a third output, the input of the adaptation circuitry coupled to the output of the sampler circuitry, the first output of the adaptation circuitry coupled to the fourth input of the equalizer circuitry, the second output of the adaptation circuitry coupled to the fifth input of the equalizer circuitry;
• and
• clock adjustment circuitry having a first input, a second input, and an output, the first input of the clock adjustment circuitry coupled to the clock output of the CDR circuitry, the second input of the clock adjustment circuitry coupled to the third output of the adaptation circuitry;
• wherein the clock adjustment circuitry is configured to:
• receive a clock signal from the clock output at its first input;
• receive a clock adjustment control signal at its second input;
• and
• provide a phase-shifted version of the clock signal at its output responsive to the clock signal and the clock adjustment control signal.

A method comprising:

• receiving data via a channel;
• performing equalization operations on received data, the equalization operations resulting in equalization results;
• performing sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples;
• performing adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal;
• adjusting a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal;
• wherein adjusting the sampling clock signal relative to the CDR clock signal responsive to the clock adjustment control signal includes adjusting a voltage of the sampling clock signal relative to a voltage of the CDR clock signal responsive to the clock adjustment control signal.