Logic drive using standard commodity programmable logic IC chips
AssigneeiCometrue Company Ltd.
InventorsJin-Yuan Lee, Mou-Shiung Lin
Life of this patent
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Abstract
An expandable logic scheme based on a chip package, includes: an interconnection substrate comprising a set of data buses for use in an expandable interconnection scheme, wherein the set of data buses is divided into a plurality of data bus subsets; and a first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprising a plurality of first I/O ports coupling to the set of data buses and at least one first I/O-port selection pad configured to select a first port from the plurality of first I/O ports in a first clock cycle to pass a first data between a first data bus subset of the plurality of data bus subsets and the first field-programmable-gate-array (FPGA) integrated-circuit (IC) chip.
Claims40
A chip package comprising:
- a first interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer and an insulating dielectric layer between the first and second interconnection metal layers;
- a first semiconductor chip over the first interconnection scheme, wherein the first interconnection scheme is under the first semiconductor chip and across an edge of the first semiconductor chip, and wherein a power supply voltage of the first semiconductor chip is smaller than or equal to 0.7 volts;
- a plurality of first metal bonds vertically under the first semiconductor chip and between the first semiconductor chip and first interconnection scheme, wherein each of the plurality of first metal bonds couples the first semiconductor chip to the first interconnection scheme;
- a second semiconductor chip over the first semiconductor chip;
- a plurality of second metal bonds vertically over the first semiconductor chip, vertically under the second semiconductor chip and between the first and second semiconductor chips;
- and
- a plurality of metal bumps under the first interconnection scheme and at a bottom of the chip package.
A chip package comprising:
- an interconnection scheme comprising a first interconnection metal layer, a second interconnection metal layer over the first interconnection metal layer and an insulating dielectric layer between the first and second interconnection metal layers;
- a first semiconductor chip over the interconnection scheme, wherein the interconnection scheme is under the first semiconductor chip and across an edge of the first semiconductor chip, and wherein a power supply voltage of the first semiconductor chip is smaller than or equal to 0.7 volts;
- a plurality of first metal bonds vertically under the first semiconductor chip and between the first semiconductor chip and interconnection scheme, wherein each of the plurality of first metal bonds couples the first semiconductor chip to the interconnection scheme;
- a second semiconductor chip over the interconnection scheme and at a same horizontal level as the first semiconductor chip, wherein the interconnection scheme is under the second semiconductor chip and across an edge of the second semiconductor chip and couples the first semiconductor chip to the second semiconductor chip;
- a plurality of second metal bonds vertically under the second semiconductor chip and between the second semiconductor chip and interconnection scheme, wherein each of the plurality of second metal bonds couples the second semiconductor chip to the interconnection scheme;
- and
- a plurality of metal bumps under the interconnection scheme and at a bottom of the chip package.
Dependencies are inferred from the claim text.