Clock signal synchronization circuit, semiconductor memory device including clock signal synchronization circuit, and method of operating clock signal synchronization circuit

A semiconductor memory device comprising a plurality of memory cells, the semiconductor memory device comprising:

• an input buffer configured to receive an external clock signal and configured to output a reference clock signal;
• and
• a clock signal synchronization circuit configured to delay the reference clock signal based on a delay control signal to generate an output clock signal that is synchronized with the reference clock signal,
• wherein the clock signal synchronization circuit comprises a replica circuit configured to delay the output clock signal and configured to output a feedback clock signal, and a delay control circuit configured to generate the delay control signal based on a phase difference between the reference clock signal and the feedback clock signal, and
• wherein the replica circuit comprises a plurality of delay cells and is configured to delay the output clock signal with different predetermined amounts of delay in response to various operation modes of a memory device using the plurality of delay cells to output the feedback clock signal.

A method of operating a clock signal synchronization circuit comprising a delay line and a replica circuit, the method comprising:

• outputting an output clock signal based on the delay line delaying an input clock signal in response to a delay control signal in a first operation mode of a memory device;
• and
• outputting a feedback clock signal by the replica circuit delaying the output clock signal using a plurality of delay cells of the replica circuit to output the feedback clock signal used for generation of the delay control signal, wherein a delay of the output clock signal differs by a different predetermined amount responsive to a change to a second operation mode of the memory device, and
• wherein the replica circuit comprises the plurality of delay cells.