3D semiconductor device and structure with three levels and isolation layers
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Deepak C. Sekar, Brian Cronquist
Life of this patent
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Abstract
A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.
Claims20
A 3D semiconductor device, the device comprising:
- a first level comprising single crystal first transistors, a first metal layer, and a first isolation layer;
- a second level comprising second transistors and a second isolation layer,
- wherein said first level is overlaid by said second level;
- a third level comprising single crystal third transistors,
- wherein said second level is overlaid by said third level,
- wherein said third level comprises a third isolation layer,
- wherein said third level is bonded to said second level;
- and
- a direct power delivery path to said second transistors,
- wherein at least a portion of said direct power delivery path is connected to at least one of said first transistors.
A 3D semiconductor device, the device comprising:
- a first level comprising single crystal first transistors, a first metal layer, and a first isolation layer;
- a second level comprising second transistors and a second isolation layer,
- wherein said first level is overlaid by said second level, and
- wherein said second transistors comprise single crystal material;
- a third level comprising single crystal third transistors,
- wherein said second level is overlaid by said third level,
- wherein said third level comprises a third isolation layer,
- wherein said third level is bonded to said second level, and
- wherein at least one of said second transistors comprises a metal gate;
- and
- a direct power delivery path to said second transistors,
- wherein at least a portion of said direct power delivery path is connected to at least one of said first transistors.
A 3D semiconductor device, the device comprising:
- a first level comprising single crystal first transistors, a first metal layer, and a first isolation layer;
- a second level comprising second transistors, and a second isolation layer,
- wherein said first level is overlaid by said second level;
- a third level comprising single crystal third transistors,
- wherein said second level is overlaid by said third level,
- wherein said third level comprises a third isolation layer,
- wherein said third level is bonded to said second level,
- wherein said second level comprises an array of memory cells;
- and
- a direct power delivery path to said second transistors,
- wherein at least a portion of said direct power delivery path is connected to at least one of said first transistors, and
- wherein at least one of said second transistors comprises hafnium oxide.
Dependencies are inferred from the claim text.