Apparatuses and methods for configurable ECC modes
AssigneeMicron Technology, Inc.
InventorsScott E. Smith, Sujeet Ayyapureddi
Life of this patent
Estimating the term…
Abstract
Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.
Claims20
An apparatus comprising:
- a first data column plane comprising a first bit line;
- a second data column plane comprising a second bit line;
- an extra column plane comprising a third bit line;
- a column decoder configured to, as part of an access operation, activate the first bit line, and activate at least one of the second bit line or the third bit line;
- and
- an error correction code (ECC) circuit configured to, as part of the access operation:
- access data bits along the first bit line,
- in a first mode, access additional data bits along the second bit line and parity bits along the third bit line, and
- in a second mode, access the parity bits along the activated one of the second or third bit line.
An apparatus comprising:
- a memory bank comprising:
- a first plurality of column planes;
- a second plurality of column planes;
- and
- an extra column plane;
- and
- a column decoder configured to select the first or the second plurality of column planes based on a column address received as part of an access operation, wherein as part of the access operation data bits are accessed in the selected one of the first or the second plurality of column planes, and based on the column address, parity bits are accessed in one of the extra column plane or the non-selected one of the first or the second plurality of column planes, wherein in a first mode, additional data bits are accessed in the other one of the first or the second plurality of column planes and the parity bits are accessed in the extra column plane, and wherein in a second mode, the parity bits are accessed in the second plurality of column planes or the extra column plane.
A method comprising:
- receiving a column address as part of an access operation;
- accessing data bits from columns in a first portion of a plurality of data column planes as part of the access operation based on the column address;
- and
- based on the column address, accessing parity bits from one of a column in a column plane not in the first portion of the plurality of data column planes or in a column of an extra column plane as part of the access operation,
- wherein in a first mode, accessing additional data bits from the one of the column in the column plane in the first portion of the plurality of data column planes and the parity data bits in the column of the extra column plane, and
- wherein in a second mode, accessing the parity data bits from the one of the volume in the column plane not in the first portion of the plurality of data column planes or in the column of the extra column plane.
Dependencies are inferred from the claim text.