Reducing disturbance in crossbar array circuits

A crossbar array circuit, comprising:

• one or more bit lines;
• one or more word lines;
• one or more cell devices connected between the bit lines and the word lines, wherein each of the cell devices comprises a Resistive Random-Access Memory (RRAM) device;
• one or more analog-to-digital converters (ADCs) connected to the one or more bit lines;
• one or more digital-to-analog converters (DACs) connected to the one or more word lines;
• one or more access control devices connected to the one or more cell devices through the one or more bit lines and configured to select a cell device in the one or more cell devices and to program the selected cell device;
• a first slew-rate controller connected to the one or more bit lines, wherein the first slew-rate controller is configured to receive an input signal or a bias and output a first slew-rate controlled signal to the one or more bit lines;
• and
• a second slew-rate controller connected between the one or more DACs and an input register, wherein the second slew-rate controller is configured to receive a signal from the input register and output a second slew-rate controlled signal to the DACs, and wherein the one or more DACs provide a voltage corresponding to the second slew-rate controlled signal to a word line of the one or more word lines that is connected to the selected cell device.