Spike based programming of a memory cell to reset state

A system comprising:

• a storage device controller;
• and
• at least one memory chip coupled to the storage device controller, wherein a memory chip comprises:
• a three dimensional crosspoint memory array comprising:
• a plurality of memory cells, a memory cell of the plurality of memory cells comprising a phase change material (PM) region and a select device (SD) region in series with the PM region;
• and
• a first address line and a second address line coupled to the memory cell;
• and
• memory controller circuitry to interface with the first address line and the second address line, the memory controller circuitry to encode a state in the memory cell by applying, through the first address line and second address line, a current spike and a programming pulse to the memory cell to cause the PM region to be placed into an amorphous state and the SD region of the memory cell to be placed into a high threshold voltage state, wherein the programming pulse has an amplitude between 70% and 95% of an amplitude of a melting current of the PM region.