Electronic circuit that renders a changed FPGA usable without changing firmware
AssigneeToshiba Tec Kabushiki Kaisha
InventorZhichao Zheng
Life of this patent
Estimating the term…
Abstract
Provided is an electronic circuit that makes a changed FPGA usable without changing firmware. The electronic circuit includes: a processor; a first field-programmable gate array (FPGA); a first generation circuit; and a second generation circuit. The first FPGA executes configuration according to first bitstream data before the processor is activated. The first generation circuit outputs a first reset signal that resets the processor to the processor based on a first completion signal indicating that the configuration is completed. The second generation circuit outputs a second completion signal indicating that the configuration is completed to the processor based on a control signal output from the processor.
Claims12
An electronic circuit, comprising:
- a processor;
- a first field-programmable gate array (FPGA) configured to execute configuration according to first bitstream data before the processor is activated;
- a first generation circuit configured to output a first reset signal that resets the processor to the processor based on a first completion signal indicating that the configuration is completed;
- and
- a second generation circuit configured to output a second completion signal indicating that the configuration is completed to the processor based on a control signal output from the processor, wherein
- the first FPGA is set in a mode of reading the first bitstream data stored in a first memory component
- the electronic circuit further comprising a second memory component configured to store second bitstream data, wherein the first FPGA executes the configuration of loading the first bitstream data read from the first memory component, wherein
- the processor outputs, to the second generation circuit, the control signal that instructs execution of configuration based on the second bitstream data, and wherein
- when a specified period elapses after the second completion signal is output, the second generation circuit outputs, to the processor, a second reset signal indicating that the first FPGA is reset.
A method for an electronic circuit, comprising:
- executing configuration using a first field-programmable gate array (FPGA) according to first bitstream data before a processor is activated;
- outputting, using a first generation circuit, a first reset signal that resets the processor to the processor based on a first completion signal indicating that the configuration is completed;
- outputting, using a second generation circuit, a second completion signal indicating that the configuration is completed to the processor based on a control signal output from the processor;
- setting the first FPGA in a mode of reading the first bitstream data stored in a first memory component;
- storing second bitstream data in a second memory component;
- and
- executing, by the first FPGA, the configuration of loading the first bitstream data read from the first memory component;
- outputting, to the second generation circuit, the control signal that instructs execution of configuration based on the second bitstream data;
- and
- when a specified period elapses after the second completion signal is output, outputting to the processor a second reset signal indicating that the first FPGA is reset.
A method of making a changed first field- programmable gate array (FPGA) usable without changing related firmware, comprising:
- executing configuration using a first FPGA according to first bitstream data before a processor is activated;
- outputting, using a first generation circuit, a first reset signal that resets the processor to the processor based on a first completion signal indicating that the configuration is completed;
- outputting, using a second generation circuit, a second completion signal indicating that the configuration is completed to the processor based on a control signal output from the processor;
- and
- when a specified period elapses after the second completion signal is output, outputting to the processor a second reset signal indicating that the first FPGA is reset.
Dependencies are inferred from the claim text.