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US 12,475,060 B2Granted
Method and apparatus for implied bit handling in floating point multiplication
AssigneeTexas Instruments Incorporated
InventorsMujibur Rahman, Timothy David Anderson
Life of this patent
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Abstract
Devices and methods are provided for performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers. In an example, a device includes a processor that includes a multiply circuit. The multiply circuit is configured to multiply floating point numbers in response to a floating point multiply instruction, and is further configured to determine values of implied bits of mantissas of the floating point numbers, and multiply the mantissas in parallel with the determining operation.
Claims20
A device comprising:
- a processor including a multiply circuit;
- wherein the multiply circuit is configured to multiply floating point numbers in response to a floating point multiply instruction, the multiply circuit including:
- first circuitry configured to determine values of implied bits of mantissas of the floating point numbers and generate first partial product terms;
- second circuitry including an array of multipliers coupled in parallel with the first circuitry and configured to multiply remainders of the mantissas to generate second partial product terms;
- and
- a set of multiplexers coupled to the first circuitry and to the second circuitry, the set of multiplexers configured to align outputs of the first circuitry and the second circuitry for providing a product of the floating point numbers.
3 more elements
A device comprising:
- a first circuit configured to multiply a first operand that includes a first exponent and a first mantissa by a second operand that includes a second exponent and a second mantissa, wherein:
- the first mantissa includes a specified portion and an implied portion;
- and
- the second mantissa includes a specified portion and an implied portion;
- and
- the first circuit includes:
- a set of second circuits coupled to receive the specified portion of the first mantissa and the specified portion of the second mantissa and configured to determine a first set of partial product terms based on the specified portion of the first mantissa and the specified portion of the second mantissa;
- a third circuit configured to determine the implied portion of the first mantissa and the implied portion of the second mantissa;
- a fourth circuit coupled to the third circuit and configured to determine a second set of partial product terms based on the implied portion of the first mantissa and the implied portion of the second mantissa;
- and
- a fifth circuit including a set of multiplexers coupled to the set of second circuits and the fourth circuit such that the third circuit and the fourth circuit are coupled in parallel with the set of second circuits, wherein the fifth circuit is configured to provide a product of the first operand and the second operand based on the first set of partial product terms and the second set of partial product terms.
8 more elements
A method comprising:
- decoding, by a decoder, a floating point multiply instruction to generate a decoded floating point multiply instruction;
- and
- multiplying, by a multiply circuit in a data path of a processor, floating point numbers responsive to the decoded floating point multiply instruction, the multiplying including performing the following operations in parallel:
- determining, by first circuitry, values of implied bits of mantissas of the floating point numbers, and generating, by the first circuitry, first partial product terms, and
- multiplying, by second circuitry that includes an array of multipliers, remainders of the mantissas to generate second partial product terms;
- and
- aligning, by a set of multiplexers, outputs of the first circuitry and the second circuitry for providing a product of the floating point numbers.
4 more elements
Dependencies are inferred from the claim text.