High-temporal-accuracy power glitch fault injection method and apparatus for cryptographic chip

A high-temporal-accuracy power glitch fault injection method for a cryptographic chip, being used for a safety test of the cryptographic chip and implemented based on a power glitch fault injection apparatus, the power glitch fault injection apparatus comprising a computer, a high-voltage pulse generator and a circuit board, and the method comprising the following steps:

• setting parameters of the power glitch fault injection apparatus, wherein the parameters specifically comprise:
• a power voltage:
• controlling the circuit board by the computer to set the power voltage according to a voltage required for the normal operation of a circuit of a cryptographic chip to be tested,
• a power glitch voltage:
• controlling the high-voltage pulse generator by the computer to set the glitch voltage according to the power voltage, and
• a power glitch length:
• controlling the high-voltage pulse generator by the computer to set the power glitch length according to the power voltage;
• performing initialized configuration on the cryptographic chip to be tested by the computer, comprising:
• power-on and plaintext input;
• determining a power glitch fault injection time according to the power glitch voltage and a target instruction, specifically comprising:
• determining a rise time of a power glitch fault according to the power glitch voltage, determining a peak moment of the power glitch fault according to the target instruction, and taking a difference value between the peak moment of the power glitch fault and the rise time of the power glitch fault as a single power glitch fault injection time;
• setting the power glitch fault injection time by the computer, and controlling the high-voltage pulse generator to generate the power glitch fault;
• injecting the power glitch fault into the cryptographic chip to be tested, determining whether the injection is an effective injection, recording an incorrect ciphertext generated by the injection as an effective incorrect ciphertext and a result that the injection is the effective injection if the injection is the effective injection, otherwise, skipping recording, wherein the power glitch fault injection comprises:
• a single power glitch fault injection and a continuous power glitch fault injection;
• after completing one fault injection by the power glitch fault injection apparatus, returning to the step of setting the parameters of the power glitch fault injection apparatus, and re-performing power glitch fault injection until preset fault injection times are reached, and obtaining effective incorrect ciphertexts generated when the cryptographic chip to be tested inputs different plaintexts;
• and
• analyzing the effective incorrect ciphertexts according to a differential fault analysis algorithm and cracking key information of the cryptographic chip to be tested to complete the safety test of the cryptographic chip;
• wherein after performing initialized configuration on the cryptographic chip to be tested by the computer, the method further comprises:
• obtaining a correct ciphertext of the cryptographic chip to be tested;
• wherein the injecting the power glitch fault into the cryptographic chip to be tested and determining whether the injection is an effective injection specifically comprises:
• injecting the power glitch fault into the cryptographic chip to be tested, determining whether the cryptographic chip to be tested outputs an incorrect ciphertext skipping the target instruction, determining the injection is the effective injection if the incorrect ciphertext skipping the target instruction is output, otherwise, the injection is a non-effective injection;
• wherein the analyzing the effective incorrect ciphertexts according to the differential fault analysis algorithm and cracking key information of the cryptographic chip to be tested specifically comprises:
• calculating a difference set according to a correct ciphertext output by the cryptographic chip to be tested under a certain plaintext and an effective incorrect ciphertext output by the cryptographic chip to be tested under the plaintext;
• repeating the above step to obtain all difference sets of the cryptographic chip to be tested under different plaintexts;
• calculating an intersection according to all the difference sets;
• and
• determining the key information of the cryptographic chip to be tested according to the intersection.