Method of interleaved processing on a general-purpose computing core

A programmable data processing apparatus, comprising

• a combined data processing and storage unit comprising
• a data processing unit comprising at least one arithmetic logic unit capable of executing data-transforming operations specified by an instruction set architecture of the apparatus, including at least one of arithmetic, logic, or other foundational data-transforming operations on data of all data types supported by the apparatus as per the instruction set architecture of the apparatus, and
• a storage unit for storing data and code pertaining to said operations, wherein at least one part of a memory of the storage unit comprises a parallel memory that includes at least one plurality of memory systems wherein, the memory systems of the plurality are random access memory systems, and jointly provide at least one unified memory address space of the plurality which is accessible through the instruction set architecture of the apparatus, and in which accesses to said plurality can be executed at memory addresses of said unified memory address space, and
• a programmable control unit for executing further operations specified by the instruction set architecture, including at least one of a pointer dereference, data fetch, data store, comparison, instruction fetch, decode, dispatch or branch,
• the control unit being adapted to, under control by code fetched from the storage unit in at least one operational mode of the apparatus, fetch operand data from the parallel memory of the storage unit and to control the data processing unit by specifying at least one of the data-transforming operations to be performed, the operand data to be processed by said data-transforming operations, and destination addresses for results of said data-transforming operations,
• characterized in that
• the apparatus is configured to, in at least one operational mode, execute a parallel random access to the parallel memory comprising at least one plurality of accesses to the parallel memory executed in parallel, wherein per each access individually, as per the instruction set architecture of the apparatus, a memory system of the parallel memory and a memory address located within said memory system are selected, said selection defining the memory access location for the execution of the data access.