US 12,474,891 B2Granted

Cryptographic architecture for cryptographic permutation

AssigneePQShield Ltd

InventorMarkku-Juhani Olavi Saarinen

Life of this patent

Estimating the term…

Loading patent…

Abstract

Cryptographic methods and systems are described. Certain examples relate to performing cryptographic operations that involve a cryptographic permutation. The methods and systems may be used to provide cryptographic functions such as hashing, encryption, decryption and random number generation. In one example, a cryptographic architecture is provided. The cryptographic architecture has a processor interface comprising a set of cryptographic registers, where the processor interface is accessible by at least one processing unit. The cryptographic architecture also has a cryptographic permutation unit comprising circuitry to perform a cryptographic permutation using data stored within the set of cryptographic registers. In examples, the at least one processing unit instructs the cryptographic permutation and accesses a result of the cryptographic permutation using the processor interface.

Claims15

Dependent claims

A cryptographic architecture comprising:

a processor interface comprising a set of cryptographic registers, the processor interface being accessible by at least one processing unit, the at least one processing unit being separate from the cryptographic architecture;
and
cryptographic permutation circuitry configured to perform a cryptographic permutation using data stored within the set of cryptographic registers,
wherein the at least one processing unit instructs the cryptographic architecture to perform the cryptographic permutation and accesses a result of the cryptographic permutation using the processor interface,
wherein the set of cryptographic registers comprise:
one or more control registers that are accessible to the at least one processing unit;
a permutation state register to store a permutation state;
a permutation input register to store permutation input data, the permutation input register being writable by the at least one processing unit;
a permutation output register to store output data, the permutation output register being readable by the at least one processing unit, wherein the permutation state is not visible to the at least one processing unit;
a mask input register to store an input mask, the mask input register being writable by the at least one processing unit;
permutation masking circuitry, communicatively coupled to the mask input register and the permutation state register, to apply an AND operation to data derived from the input mask and data derived from permutation data from the permutation state register;
and
input application circuitry, communicatively coupled to the permutation masking circuitry and the permutation input register, to apply an XOR operation to data derived from the permutation masking circuitry and data derived from the permutation input data, the input application circuitry being configured to supply output data to the cryptographic permutation circuitry;
wherein the cryptographic architecture is configured to indicate a completion of the cryptographic permutation by setting a control flag within the control registers.

11 more elements

A method of performing a cryptographic operation comprising:

receiving, at a cryptographic architecture, an instruction to perform the cryptographic operation from a processing unit, the processing unit being separate from the cryptographic architecture, the cryptographic architecture comprising a set of cryptographic registers comprising one or more control registers that are accessible to the at least one processing unit, wherein receiving said instruction comprises:
accessing a control register of the cryptographic architecture to determine whether a start flag has been set by the processing unit to indicate a start of the cryptographic operation;
loading, by a cryptographic permutation circuitry of the cryptographic architecture, a permutation state from a permutation state register;
loading, by the cryptographic permutation circuitry, permutation input data from a permutation input register, the permutation input data being written under the control of the processing unit;
loading, by the cryptographic permutation circuitry, mask input data from a mask input register;
updating, by the cryptographic architecture, the permutation state in the permutation state register of the set of cryptographic registers by performing an XOR operation as a function of the permutation input data and a result of an AND operation performed on the mask input data and the permutation state to generate updated data;
performing, using the cryptographic permutation circuitry, a cryptographic permutation on the updated data;
storing, by the cryptographic architecture, an output of the cryptographic permutation into the permutation state register;
and
indicating, by the cryptographic architecture, to the at least one processing unit that the permutation is complete, wherein the processing unit accesses the output of the cryptographic permutation from the set of cryptographic registers, said indicating comprising setting a control flag within the control registers.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/576,299Filed 14 Jan 2022 · continuation
Priority: GB 191037219 Jul 2019
Published: US 2022/0138349 A15 May 2022
Granted: 18 Nov 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

G06F 7/584
Pseudo-random number generators: using finite field arithmetic, e.g. using a linear feedback shift register
G06F 7/768
Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data: data…
G06F 9/30029
To perform operations on data operands: logical and Boolean instructions, e.g. XOR, NOT
G06F 9/30032
To perform operations on data operands: movement instructions, e.g. move, shift, rotate, shuffle