System access boundary scan via system sideband signal connections
AssigneeMicron Technology, Inc.
InventorMichael Richard Spica
Life of this patent
Estimating the term…
Abstract
A method performed by automated test equipment (ATE) includes power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface; communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode; sending a command to cause the memory controller IC to place the PCB interface in a boundary scan mode; remapping a portion of pins of the PCB interface to a boundary scan interface; and communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.
Claims20
A method performed by automated test equipment (ATE), the method comprising:
- power cycling a solid state drive (SSD) device under test by the ATE, wherein the SSD device includes a memory controller integrated circuit (IC) attached to a printed circuit board (PCB) having a PCB interface;
- communicating one or more signals between the ATE and the memory controller IC using the PCB interface in a normal system mode;
- sending, by the ATE, a command to cause the memory controller IC to place the PCB interface in a boundary scan mode;
- remapping a portion of pins of the PCB interface to a boundary scan interface;
- and
- communicating one or more boundary scan signals between the ATE and the memory controller IC using the remapped portion of pins of the PCB interface in the boundary scan mode.
A memory device without dedicated input-output (I/O) for boundary scan, the device comprising:
- a printed circuit board (PCB);
- an input-output (I/O) connector;
- and
- a memory controller integrated circuit (IC) mounted on the (PCB) and connected to the I/O connector, wherein the memory controller IC includes:
- first circuitry to receive normal operating signals on first pins of the I/O connector when the memory controller is in a normal operating mode;
- and
- boundary scan circuitry to receive one or more boundary scan signals on the same first pins of the I/O connector when the memory controller is in a boundary scan mode.
Automated test equipment (ATE) to test a solid state drive (SSD) device, the ATE comprising:
- first physical layer (PHY) circuitry and boundary scan PHY circuitry;
- a test connector having pins to connect to a solid state disk (SSD) device under test;
- multiplexer circuitry connected to the first PHY circuitry, the boundary scan PHY circuitry, and the test connector;
- and
- a tester controller connected to the first PHY circuitry and the boundary scan PHY circuitry, and configured to:
- communicate one or more signals from the first PHY circuitry to the SSD device under test in a normal mode using first pins of the test connector,
- communicate, using the test connector, a command to the SSD device under test to enter a boundary scan mode;
- and
- communicate one or more boundary scan commands from the boundary scan PHY circuitry to the SSD device under test in the boundary scan mode using the same first pins of the test connector.
Dependencies are inferred from the claim text.