EEG impedance test circuit, method, and device

An electroencephalogram (EEG) impedance test circuit, comprising:

• a frequency selecting circuit, an amplification circuit, a follower circuit, and a power supply terminal, wherein, an input end of the frequency selecting circuit is connected to the power supply terminal, the input end of the frequency selecting circuit is further connected to an input end of the amplification circuit, an output end of the frequency selecting circuit is connected to an output end of the amplification circuit, and the output end of the amplification circuit is connected to an input end of the follower circuit;
• the frequency selecting circuit is configured for oscillating to generate an oscillation signal;
• the amplification circuit is configured for amplifying the oscillation signal;
• and
• the follower circuit is configured for isolating the frequency selecting circuit and the amplification circuit;
• wherein a frequency of the oscillation signal does not comprise n*50 HZ, n is an integer greater than or equal to 1.