Low voltage differential signaling receiver

A low voltage differential signaling receiver, comprising:

• a resistor load pair;
• an input stage, comprising:
• a P-type transistor pair, coupled to the resistor load pair, the P-type transistor pair being configured to generate first differential output voltages on the resistor load pair according to differential input signals;
• a N-type transistor pair, coupled to the resistor load pair, the N-type transistor pair being configured to generate the first differential output voltages on the resistor load pair according to the differential input signals;
• a current mode logic stage, coupled to the resistor load pair and the input stage, the current mode logic stage being configured to enhance a gain of the first differential output voltages into second differential output voltages;
• a latch circuit, coupled to the current mode logic stage, the latch circuit being configured to generate third differential output voltages according to the second differential output voltages and latch the third differential output voltages;
• and
• a comparator circuit, coupled to the latch circuit, the comparator circuit being configured to compare the third differential output voltages and generate a single-ended output signal.