Low latency retimer and low latency control method

A low latency control method, wherein, the method is applied to a retimer, the retimer comprises two physical layer modules comprising a first physical layer module on a first side of a chip package of the retimer, and a second physical layer module provided on a second side of the chip package opposite to the first side, each physical layer module comprises at least one set of signal transceiver units comprising a signal receiving unit and a signal transmitting unit;

• wherein for each set of the signal transceiver units on the first side of chip package, the signal receiving unit has a first signal pin, and the signal transmitting unit has a second signal pin, one of the first signal pin and the second signal pin is connected to a first chip package pin on the first side of the chip package, and the other of the first signal pin and the second signal pin is connected to a second chip package pin on the second side of the chip package;
• wherein for each set of the signal transceiver units, the low latency control method comprises:
• by the signal receiving unit, upon receiving a first high-speed serial signal, performing a serial-to-parallel conversion on the first high-speed serial signal to generate a parallel signal and sending the parallel signal to the signal transmitting unit;
• and
• by the signal transmitting unit, performing a parallel-to-serial conversion on the parallel signal, converting the parallel signal to a second high-speed serial signal, and outputting the second high-speed serial signal.