AD conversion device

An AD conversion device comprising:

• an AD converter to convert an analog signal into digital data for every sampling point based on a sampling frequency and to output the digital data as sampling data for every sampling point;
• a controller including a buffer memory in which the sampling data from the AD converter is temporarily stored in time series and from which the sampling data is read out in time series, and a decimation controller, wherein the decimation controller monitors whether or not the analog signal contains a high-frequency component, when the analog signal contains the high-frequency component, uses a sampling point in the sampling data from the AD converter, containing the high-frequency component, as a reference point, sets a region including a first region and a second region as a high-speed sampling region, the first region having the reference point and sampling points before and after the reference point, the first region having a decimation rate of 1, the second region being continuous with the first region, the second region having sampling points, and in the second region, sampling being performed at a decimation rate of 1/N1 for selecting one sampling point from N1 sampling points, the N1 having a value smaller than the N0, sets a region other than the high-speed sampling region, as a decimation region in which sampling is performed at a decimation rate of 1/N0 for selecting one sampling point for every N0 sampling points, outputs a write-enable signal indicating write-enabled for sampling data at the selected sampling point for every N0 sampling points among the sampling points in the decimation region, sampling data at all sampling points in the high-speed sampling region, and sampling data at the selected sampling point for every N1 sampling points among the sampling points in the second region, and outputs decimation bit information indicating whether the sampling data is sampling data at a sampling point in the decimation region or sampling data at a sampling point in the high-speed sampling region;
• and
• a storage circuit to receive the sampling data stored in the buffer memory, the write-enable signal and the decimation bit information from the decimation controller, and to store the sampling data stored in the buffer memory at a sampling point at which the write-enable signal indicating write-enabled is received from the decimation controller and the decimation bit information from the decimation controller in association with each other,
• wherein the decimation controller includes:
• a trigger determiner to monitor whether or not the analog signal contains a high-frequency component with sampling data from the AD converter, and to detect a sampling point in the sampling data containing the high-frequency component as a trigger point;
• a counter to operate with the N0 as an upper limit value of a count value and to output the count value;
• and
• a decimation determiner to use a reference point of the high-speed sampling region as the trigger point detected by the trigger determiner, and to determine the selected sampling point for every N1 sampling points among the sampling points in the second region with a count value from the counter, and to determine the selected sampling point for every N0 sampling points among the sampling points in the decimation region with the count value from the counter, and
• the buffer memory stores the count value from the counter for every sampling point in association with the sampling data from the AD converter.