High bandwidth memory stack with side edge interconnection and 3D IC structure with the same

An IC structure comprising:

• a first memory stack comprising:
• a plurality of semiconductor dies horizontally separate from each other, wherein each semiconductor die comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls comprising a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads arranged along the first sidewall;
• wherein the area of the bottom surface or the top surface of each semiconductor die is larger than that of any sidewall;
• and
• a logic die with memory controller under the first memory stack and electrically connected to the plurality of edge pads of each semiconductor die;
• a logic die with processor circuit disposed over and electrically connected to the logic die with memory controller;
• and
• a packaging substrate under and electrically connected to the logic die with memory controller,
• wherein a die area of the logic die with memory controller is larger than the sum of a horizontal cross-section area of the first memory stack and a die area of the logic die with processor circuit,
• wherein there is no interposer between the packaging substrate and the logic die with memory controller, and there is no TSV in any semiconductor die of the first memory stack.