3D semiconductor device and structure with metal layers and memory cells

A 3D semiconductor device, the device comprising:

• a first level comprising a first single crystal layer, said first level comprising first transistors,
• wherein each of said first transistors comprises a single crystal channel;
• a first metal layer;
• a second metal layer overlaying said first metal layer;
• a second level comprising a plurality of second transistors, said second level overlaying said first level;
• a third level comprising a plurality of third transistors, said third level overlaying said second level;
• a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level,
• wherein said second level comprises a plurality of first memory cells,
• wherein each of said plurality of first memory cells comprises at least one of said second transistors,
• wherein said fourth level comprises a plurality of second memory cells,
• wherein each of said plurality of second memory cells comprises at least one of said fourth transistors,
• wherein said first level comprises memory control circuits,
• wherein at least one of said second transistors comprises a metal gate,
• wherein said memory control circuits control writing to said plurality of second memory cells, and
• wherein said first level comprises a plurality of Through Silicon Via (“TSV”).

A 3D semiconductor device, the device comprising:

• a first level comprising a first single crystal layer, said first level comprising first transistors,
• wherein each of said first transistors comprises a single crystal channel;
• a first metal layer;
• a second metal layer overlaying said first metal layer;
• a second level comprising a plurality of second transistors, said second level overlaying said first level;
• a third level comprising a plurality of third transistors, said third level overlaying said second level;
• and
• a fourth level comprising a plurality of fourth transistors, said fourth level overlaying said third level,
• wherein said second level comprises a plurality of first memory cells,
• wherein each of said plurality of first memory cells comprises at least one of said second transistors,
• wherein said fourth level comprises a plurality of second memory cells,
• wherein each of said plurality of second memory cells comprises at least one of said fourth transistors,
• wherein said first level comprises memory control circuits,
• wherein at least one of said second transistors comprises a metal gate,
• wherein said memory control circuits control reading from said plurality of second memory cells,
• wherein said memory control circuits control writing to said plurality of third memory cells, and
• wherein said first level is bonded to said second level.