Semiconductor test apparatus capable of inducing reduction of power consumption
AssigneeYC Corporation
InventorsHyo Sang Jo, Wan Soon Park, Yong Hyun Kim, Jae Hoon Joo
Life of this patent
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Abstract
A semiconductor test apparatus is provided. The semiconductor test apparatus includes: a test management unit determining a test mode, generating a test signal in accordance with the determined test mode, and transmitting the test signal to fail memories; and one or more fail memory boards including the fail memory, which store fail signals generated as a result of a test conducted in accordance with the test signal and address information of the fail signals, wherein if the determined test mode is a first test mode, at least some of the failure memory boards are powered off.
Claims20
A semiconductor test apparatus comprising:
- a test management unit configured to determine a test mode, generate a test signal in accordance with the determined test mode, and transmit the test signal to fail memories, the fail memories configured to store fail signals generated as a result of a test conducted in accordance with the test signal and address information of the fail signals;
- and
- one or more fail memory boards including the fail memories,
- wherein the test management unit is further configured to cause at least some of the fail memory boards to be powered off if the determined test mode is a first test mode.
A semiconductor test apparatus comprising:
- a test management unit is configured to generate a test signal in accordance with a test program, transmit the test signal to fail memories, calculate an amount of input/output (I/O) usage in connection with the an execution of the test program, and determine whether to generate a first control signal based on the calculated amount of I/O usage;
- and
- a plurality of fail memory boards including fail memory, which include fail signals generated as a result of a test conducted in accordance with the test signal and address information of the fail signals,
- wherein the test management unit is further configured to cause some of the fail memory boards to be powered off when the first control signal is generated.
Dependencies are inferred from the claim text.