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US 12,469,565 B2Granted
Fast bit erase for upper tail tightening of threshold voltage distributions
AssigneeMicron Technology, Inc.
InventorsSheyang Ning, Lawrence Celso Miranda, Tomoko Ogura Iwasaki
Life of this patent
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Abstract
A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. The control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.
Claims12
A memory device comprising:
- a memory array comprising:
- a first data line;
- a first pillar coupled with the first data line;
- a second data line;
- a second pillar coupled with the second data line;
- and
- a plurality of wordlines coupled with the first pillar and the second pillar;
- and
- control logic operatively coupled with the memory array, the control logic to perform operations comprising:
- causing the plurality of wordlines to be discharged after a program pulse is applied to program one or more memory cells coupled with a selected wordline of the plurality of wordlines;
- causing a supply voltage to be applied to the second data line to cause a voltage of the second pillar to float;
- causing a ground voltage to be applied to the first data line to inhibit soft erase associated with the selected wordline via the first pillar;
- causing a first subset of unselected wordlines of the plurality of wordlines located below the selected wordline to remain discharged;
- causing the selected wordline and a second subset of the unselected wordlines located above the selected wordline to be charged to boost channel voltages;
- and
- causing, after boosting the second subset of the unselected wordlines, one of the ground voltage or a negative voltage to be applied to the selected wordline to increase a soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline.
13 more elements
A method comprising:
- causing a plurality of wordlines to be discharged after a program pulse programs one or more memory cells coupled with a selected wordline of the plurality of wordlines;
- causing a ground voltage to be applied to a first data line to inhibit soft erase associated with the selected wordline via a first pillar that is coupled with the first data line and the plurality of wordlines;
- causing a supply voltage to be applied to a second data line to cause a voltage of a second pillar to float, the second pillar coupled with the plurality of wordlines and the first data line;
- causing a first subset of unselected wordlines of the plurality of wordlines located below the selected wordline to remain discharged;
- causing the selected wordline and a second subset of the unselected wordlines located above the selected wordline to be charged to boost channel voltages;
- and
- causing, after boosting the second subset of the unselected wordlines, one of the ground voltage or a negative voltage to be applied to the selected wordline to increase a soft erase voltage between a channel of a memory cell coupled with the second pillar and the selected wordline.
4 more elements
Dependencies are inferred from the claim text.