Serial-gate transistor and nonvolatile memory device including the same

A serial-gate transistor, comprising:

• a first source-drain region, a gate region, and a second source-drain region, wherein the first source-drain region, the gate region, and the second source-drain region are sequentially arranged in a horizontal direction at a semiconductor substrate;
• and
• a plurality of gates sequentially arranged in the horizontal direction in the gate region above the semiconductor substrate,
• wherein the plurality of gates are electrically decoupled from each other,
• wherein each gate of the plurality of gates is directly coupled to a corresponding block selection signal of a plurality of block selection signals, and
• wherein the plurality of gates are controlled independently of each other.

A nonvolatile memory device, comprising:

• a plurality of first bonding metal patterns disposed in a cell region;
• a plurality of second bonding metal patterns disposed in a peripheral region disposed under the cell region, wherein the peripheral region is vertically coupled to the cell region by the plurality of first bonding metal patterns and the plurality of second bonding metal patterns;
• a memory cell array disposed in the cell region, the memory cell array comprising a plurality of memory blocks;
• and
• a plurality of pass transistor blocks disposed in the peripheral region, each pass transistor block of the plurality of pass transistor blocks comprising a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks, each serial-gate transistor of the plurality of serial-gate transistors comprising:
• a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate;
• a plurality of gates that are sequentially arranged in the horizontal direction in the gate region above the semiconductor substrate,
• wherein the plurality of gates are electrically decoupled from each other,
• wherein each gate of the plurality of gates is directly coupled to a corresponding block selection signal of a plurality of block selection signals, and
• wherein the plurality of gates are controlled independently of each other.