Variable page size architecture
AssigneeMicron Technology, Inc.
InventorCorrado Villa
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.
Claims20
An apparatus, comprising:
- a memory array including a plurality of memory sections, each memory section having a plurality of physical rows of memory cells and a plurality of physical columns of memory cells, the plurality of memory sections including a first memory section and a second memory section linked with the first memory section;
- a set of sense components coupled with the memory array, each sense component of the set of sense components configured to couple with one or more columns of a respective set of columns of the first memory section of the memory array, and wherein each sense component of the set of sense components is configured to be selectively coupled with one of a subset of memory cells of a respective physical row of the plurality of physical rows of the first memory section;
- and
- one or more controllers coupled with the memory array and configured to generate a logic row address for accessing a first memory cell of a physical row of the plurality of physical rows of the first memory section and a second memory cell of the second memory section based at least in part on a page size associated with the memory array and the first memory section being linked with the second memory section.
An apparatus, comprising:
- processing circuitry associated with one or more memory devices and configured to cause the apparatus to:
- receive an access request for a first memory cell in a memory bank of a memory array that includes a plurality of memory sections, each memory section having a plurality of physical columns of memory cells, a plurality of physical rows of memory cells, and a set of sense components, the plurality of memory sections including a first memory section comprising the first memory cell and a second memory section comprising a second memory cell, wherein the second memory section is linked with the first memory section, and wherein each sense component of the set of sense components is configured to be selectively coupled with one of a subset of memory cells of a respective physical row of the plurality of physical rows of the first memory section;
- generate, based at least in part on receiving the access request, a logic row address associated with one or more memory cells of a memory page including the first memory cell and the second memory cell;
- and
- access the first memory cell and the second memory cell based at least in part on generating the logic row address and the first memory section being linked with the second memory section.
A method, comprising:
- receiving an access request for a first memory cell in a memory bank of a memory array that includes a plurality of memory sections, each memory section having a plurality of physical columns of memory cells, a plurality of physical rows of memory cells, and a set of sense components, the plurality of memory sections including a first memory section comprising the first memory cell and a second memory section comprising a second memory cell, wherein the second memory section is linked with the first memory section, and wherein each sense component of the set of sense components is selectively coupled with one of a subset of memory cells of a respective physical row of the plurality of physical rows of the first memory section;
- generating, based at least in part on receiving the access request, a logic row address associated with one or more memory cells of a memory page including the first memory cell and the second memory cell;
- and
- accessing the first memory cell and the second memory cell based at least in part on generating the logic row address and the first memory section being linked with the second memory section.
Dependencies are inferred from the claim text.