Signal generator for controlling timing of signal in memory device

A device, comprising:

• a first word line;
• a bit cell coupled between a first bit line and a second bit line, and coupled to the first word line;
• a first switch configured to couple the first bit line to the second bit line according to a first control signal;
• and
• a first logic gate configured to generate the first control signal according to a distance between the first logic gate and the first word line.

A device, comprising:

• a word line decoder configured to provide a word line signal according to a first control signal;
• a first logic gate configured to generate a second control signal according to a first clock signal for controlling a bit line;
• a tracking wiring, two terminals of the tracking wiring being coupled to two input terminals of the first logic gate;
• a second logic gate configured to generate the first control signal;
• a third logic gate configured to receive a second clock signal and an input control signal, an output terminal of the third logic gate being coupled to an input terminal of the second logic gate;
• and
• a fourth logic gate configured to receive the second clock signal and output the first clock signal.