Scan testing using scan frames with embedded commands
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.
Claims20
A test architecture within an integrated circuit, the test architecture comprising:
- serial input;
- serial-to-parallel circuitry coupled to the serial input and including parallel outputs;
- circuitry to be tested, wherein the circuitry to be tested is coupled to the parallel outputs of the serial-to-parallel circuitry;
- parallel-to-serial circuitry coupled to the circuitry to be tested;
- serial output coupled to the parallel-to-serial circuitry;
- a clock input;
- and
- a controller coupled to the serial input, the circuitry to be tested, and the clock input, wherein the controller is configurable to respond to a control bit embedded in a serial scan frame received via the serial input.
A test architecture within an integrated circuit, the test architecture comprising:
- serial input configured to receive a serial scan frame including a command bit and a frame marker bit embedded in the serial scan frame;
- serial output;
- a first series of shift elements;
- a second series of shift elements;
- a controller coupled to the serial input via the first series of shift elements;
- and
- circuitry to be tested,
- wherein the controller is configurable to receive the command bit and the frame marker bit from the first series of shift elements,
- wherein the circuitry to be tested is coupled to the serial input via the first series of shift elements,
- wherein the circuitry to be tested is coupled to the serial output via the second series of shift elements, and
- wherein the circuitry to be tested is coupled to the controller.
A method comprising:
- receiving, at a serial input, a scan frame including a command bit, and a frame marker bit;
- loading the scan frame into shift elements coupled to the serial input, wherein the shift elements are coupled to circuitry to be tested and a controller;
- causing, by the controller responsive to the command bit and the frame marker bit, the circuitry to be tested to perform a test operation.
Dependencies are inferred from the claim text.