Resistor with exponential-weighted trim

A method of forming an integrated circuit, comprising:

• forming a plurality of unit resistors over a semiconductor substrate;
• forming first and second interconnection buses;
• connecting a plurality of composite resistors between the first and second interconnection buses, each composite resistor of the plurality of composite resistors including a subset of the plurality of unit resistors connected in parallel or a subset of the plurality of unit resistors connected in series;
• connecting a corresponding one of a plurality of fusible links between the second interconnection bus and each of a corresponding one of the composite resistors;
• and
• connecting a unit resistor directly to the first interconnection bus and to the second interconnection bus via one of the plurality of fusible links.

A method of forming an electronic device, comprising:

• forming in or over an integrated circuit a two-dimensional array of unit resistors including a first plurality of unit resistors and a second plurality of unit resistors;
• interconnecting the first plurality of unit resistors between a first node and a second node, including connecting a first unit resistor and a second unit resistor of the first plurality of unit resistors at a third node;
• and
• interconnecting the second plurality of unit resistors between the second node and the third node,
• wherein the first plurality of unit resistors are located between a first subset of the second plurality of unit resistors and a second subset of the second plurality of unit resistors, and the unit resistors of the second plurality of unit resistors are arranged as a series of steps of a resistor ladder in which a resistance of each of the steps increases exponentially with respect to a next-lower step.

A method of forming an integrated circuit, comprising:

• forming a plurality of unit resistors in a semiconductor substrate;
• connecting a first subset N of the unit resistors in series thereby forming a first composite resistor;
• connecting a second subset N of the unit resistors in parallel thereby forming a second composite resistor;
• connecting a first terminal of the first composite resistor and a first terminal of the second composite resistor to a first interconnection bus;
• connecting a second terminal of the first composite resistor and a second terminal of the second composite resistor to a second interconnection bus;
• and
• connecting a third subset M of the unit resistors in parallel directly to the first interconnection bus and directly to the second interconnection bus.

A method of forming an integrated circuit, comprising:

• forming a plurality of unit resistors in a semiconductor substrate;
• connecting a first subset N of the unit resistors in series thereby forming a first composite resistor;
• connecting a second subset N of the unit resistors in parallel thereby forming a second composite resistor;
• connecting a first terminal of the first composite resistor and a first terminal of the second composite resistor to a first interconnection bus;
• connecting a second terminal of the first composite resistor and a second terminal of the second composite resistor to a second interconnection bus;
• and
• connecting a first terminal of a single unit resistor directly to the first interconnection bus and a second terminal of the single unit resistor to a connection node.