Nonvolatile charge trap memory device having a high dielectric constant blocking region

A nonvolatile memory transistor comprising:

• a semiconductor substrate;
• a gate structure;
• a multi-layer blocking dielectric region adjacent the gate structure;
• and
• a charge trapping region abutting the multi-layer blocking dielectric region, the charge trapping region having an oxygen-rich nitride layer and an oxygen-lean nitride layer, wherein the oxygen-lean nitride layer abuts the multi-layer blocking dielectric region, and the oxygen-rich nitride layer abuts the oxygen-lean nitride layer;
• a tunnel oxide positioned such that the charge trapping region is located between the tunnel oxide and the multi-layer blocking dielectric region, wherein the oxygen-rich nitride layer abuts the tunnel oxide;
• wherein the multi-layer blocking dielectric region includes a first dielectric layer comprising a silicon oxide and a second dielectric layer closest to the gate structure comprising a high K dielectric, wherein the first dielectric layer and the second dielectric layer are formed of different materials having different dielectric constants.