Integrated chip including a device with a reduced surface field region
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLiang-Yu Su, Chih-Wen Yao, Hsiao-Chin Tuan, Ming-Ta Lei
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Abstract
Various embodiments of the present disclosure are directed towards an integrated chip including a first doped region in a substrate and comprising a first doping type. A gate structure is over the first doped region. A pair of contact regions are in the substrate on opposing sides of the gate structure and comprising the first doping type. The first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions. A second doped region is in the substrate and along a bottom of the first doped region. The second doped region comprises a second doping type opposite the first doping type.
Claims20
An integrated chip comprising:
- a first doped region in a substrate and comprising a first doping type;
- a gate structure over the first doped region;
- a pair of contact regions in the substrate on opposing sides of the gate structure and comprising the first doping type, wherein the first doped region continuously laterally extends between the pair of contact regions and contacts the pair of contact regions;
- and
- a second doped region in the substrate and along a bottom of the first doped region, wherein the second doped region comprises a second doping type opposite the first doping type, wherein a top of the second doped region contacts or is vertically above a bottom of the pair of contact regions.
An integrated chip comprising:
- a first semiconductor device disposed on a substrate and comprising:
- a first doped region and a second doped region disposed in the substrate and laterally spaced from one another;
- a well region in the substrate laterally extending between the first and second doped regions, wherein the first doped region, the second doped region, and the well region comprise a first dopant type, wherein the well region contacts a side of the first doped region and a side of the second doped region;
- and
- a depletion enhancement region below the well region and comprising a second dopant type different from the first dopant type.
An integrated chip comprising:
- a varactor on a substrate and comprising:
- a first doped region in the substrate and comprising a first conductivity type;
- a gate structure over the first doped region;
- a pair of contact regions in the substrate and spaced on opposite sides of the gate structure, wherein the pair of contact regions comprise the first conductivity type, wherein the first doped region is arranged laterally between the pair of contact regions;
- and
- a second doped region in the substrate and below the first doped region, wherein the second doped region comprises a second conductivity type different from the first conductivity type;
- wherein the varactor is configured to be in a depletion state, wherein in the depletion state a depletion region is disposed in the substrate under the gate structure, wherein the depletion region extends from a top surface of the substrate to a top of the second doped region.
Dependencies are inferred from the claim text.